Auflistung nach Autor:in "Stechele, Walter"
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- ZeitschriftenartikelAcceleration of Optical Flow Computations on Tightly-Coupled Processor Arrays(PARS-Mitteilungen: Vol. 30, Nr. 1, 2013) Sousa, Éricles Rodrigues; Tanase, Alexandru; Lari, Vahid; Hannig, Frank; Teich, Jürgen; Paul, Johny; Stechele, Walter; Kröhnert, Manfred; Asfour, TaminOptical flow is widely used in many applications of portable mobile de- vices and automotive embedded systems for the determination of motion of objects in a visual scene. Also in roboticsit is used for motion detection, object segmentation, time-to-contact information, focus of expansion calculations, robot navigation, and automatic parking for vehicles. Similar to many other image processing algorithms, optical flow processes pixel operations repeatedly over whole image frames. Thusit provides a high degree of fine-grained parallelism which can be efficiently exploited on massively parallel processor arrays. In this contextwe propose to accelerate the computation of complex motion estimation vectors on programmable tightly-coupled processor arrays, which offer a high flexibility enabled by coarse-grained reconfiguration capabilities. Novel is also that the degree of parallelism may be adapted to the number of processors that are available to the application. Finallywe present an implementation that is 18 times faster when compared to (a) an FPGA-based soft processor implementationand (b) may be adapted regarding different QoS requirements, hence, being more flexible than a dedicated hardware implementation.
- ZeitschriftenartikelAcceleration of Optical Flow Computations on Tightly-Coupled Processor Arrays(PARS: Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware: Vol. 30, No. 1, 2013) Sousa, Éricles; Tanase, Alexandru; Lari, Vahid; Hannig, Frank; Teich, Jürgen; Paul, Johny; Stechele, Walter; Kröhnert, Manfred; Asfour, TaminOptical flow is widely used in many applications of portable mobile devices and automotive embedded systems for the determination of motion of objects in a visual scene. Also in robotics, it is used for motion detection, object segmentation, time-to-contact information, focus of expansion calculations, robot navigation, and automatic parking for vehicles. Similar to many other image processing algorithms, optical flow processes pixel operations repeatedly over whole image frames. Thus, it provides a high degree of fine-grained parallelism which can be efficiently exploited on massively parallel processor arrays. In this context, we propose to accelerate the computation of complex motion estimation vectors on programmable tightly-coupled processor arrays, which offer a high flexibility enabled by coarse-grained reconfiguration capabilities. Novel is also that the degree of parallelism may be adapted to the number of processors that are available to the application. Finally, we present an implementation that is 18 times faster when compared to (a) an FPGA-based soft processor implementation, and (b) may be adapted regarding different QoS requirements, hence, being more flexible than a dedicated hardware implementation.
- KonferenzbeitragAn architecture for runtime evaluation of soc reliability(INFORMATIK 2006 – Informatik für Menschen, Band 1, 2006) Bernauer, Andreas; Bringmann, Oliver; Rosenstiel, Wolfgang; Bouajila, Abdelmajid; Stechele, Walter; Herkersdorf, AndreasThis paper presents an architecture to evaluate the reliability of a systemon-chip (SoC) during its runtime that also accounts for the system's redundancy. We propose to integrate an autonomic layer into the SoC to detect the chip's current condition and instruct appropriate countermeasures. In the autonomic layer, error counters are used to count the number of errors within a fixed time interval. The counters' values accumulate into a global register representing the system's reliability. The accumulation takes into account the series and parallel composition of the system.
- KonferenzbeitragCombitgen: A new approach for creating partial bitstreams in virtex-II pro devices(ARCS'06, 19th International Conference on Architecture of Computing Systems, 2006) Claus, Christopher; Müller, Florian Helmut; Stechele, Walter
- ZeitschriftenartikelA Fault-Tolerant Processor Architecture(FERS-Mitteilungen: Vol. 28, No. 1, 2010) Bouajila, Abdelmajid; Sommer, Thomas; Zeppenfeld, Johannes; Stechele, Walter; Herkersdorf, Andreas
- KonferenzbeitragOptimization potential of CMOS power by wire spacing(Informatk 2005. Informatik Live! Band 1, 2005) Zuber, Paul; Müller, Florian Helmut; Stechele, WalterIn this work, we identify the power-optimal wire spacing as a geometric program. Its solution is a vector of individual distances between the wires. To quantify the optimization potential by this method we model the output of a grid based router with a set of parallel wires. A comparison of the power values before and after geometric optimization shows that the optimization potential lies well in the two digit percent zone for a representative circuit model in a 130nm process.
- KonferenzbeitragPartial reconfiguration on FPGAs in practice – tools and applications(ARCS 2012 Workshops, 2012) Koch, Dirk; Torresen, Jim; Beckhoff, Christian; Ziener, Daniel; Dennl, Christopher; Breuer, Volker; Teich, Jürgen; Feilen, Michael; Stechele, WalterRun-time reconfiguration of FPGAs has been around in academia for more than two decades but it is still applied very seldom in industrial applications. This has two main reasons: a lack of killer applications that substantially benefit from run-time reconfiguration and design tools that permit to quickly implement corresponding reconfigurable systems. This tutorial gives a survey on state-of-the-art trends on reconfigurable architectures and devices, application specific requirements, and design techniques and tools that are essential for implementing partial run-time reconfiguration on FPGAs. This is followed by a demonstration of the floorplanning and constraint generation tool GoAhead. Furthermore, the tutorial will reveal several applications that benefit from partial reconfiguration, including network data processing, digital signal processing, cognitive radio, and systems on a reconfigurable chip. For these applications, the individual challenges and implementation issues are presented together with the achieved results. This tutorial demonstrates that partial FPGA reconfiguration is beneficial and applicable in industrial systems.
- KonferenzbeitragPotentials and challenges for multi-core processors in robotic applications(INFORMATIK 2013 – Informatik angepasst an Mensch, Organisation und Umwelt, 2013) Herkersdorf, Andreas; Paul, Johny; Kumar Pujari, Ravi; Stechele, Walter; Wallentowitz, Stefan; Wild, Thomas; Zaib, AurangMulti-core processors have shown to be superior to single-core with respect to performance and power efficiency. However, multi-core imposes additional challenges on system complexity and application programming. This paper reviews benefits and challenges of multi-core processors in embedded real-time applications like humanoid robotics. Selected approaches towards enabling multi-core processors are shown, covering multiple hardware / software abstraction levels, including isolation of individual applications, differentiated quality-of-service support, thread mpping, and resource-aware programming.
- KonferenzbeitragSelf-reconfigurable control architecture for complex robots(INFORMATIK 2013 – Informatik angepasst an Mensch, Organisation und Umwelt, 2013) Hartmann, Jan; Stechele, Walter; Maehle, ErikAdvanced robot systems need to carry out increasingly complex task sets. However, they are typically optimized to a very restricted set of tasks and environments to solve demanding problems. This work will therefore propose a self-reconfigurable software and hardware architecture in order to enable the dynamic optimization of a robot system depending on the current situation, i.e. the current task, robot state, and environment. The proposed framework is based on organic computing principles and unsupervised machine learning techniques. It further uses dynamically reconfigurable Field Programmable Gate Arrays (FPGA) as hardware accelerators.
- KonferenzbeitragTowards a dynamically reconfigurable system-on-chip platform for video signal processing(ARCS 2004 – Organic and pervasive computing, 2004) Stechele, Walter; Herrmann, Stephan; Herkersdorf, AndreasThis paper reports ongoing work towards a dynamically reconfigurable System-on-Chip (SoC) platform for video signal processing. It consists of dedicated, statically and dynamically reconfigurable components, as well as an embedded RISC core and memory. Application-specific software libraries support control of dynamic reconfiguration of low level operations by high level instructions. Thus programmability is combined with high data throughput and low power consumption of hardwired circuits. Preliminary work presented here is focused on one selected application, video object segmentation. The architecture of a coprocessor for video object segmentation is presented, which exploits the basic concept of the dynamically reconfigurable SoC platform. A library of software functions for image processing was developed, too, which will be used as a starting point for the application-specific software parts of the platform.