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Auflistung nach Autor:in "Bouajila, Abdelmajid"

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  • Konferenzbeitrag
    An architecture for runtime evaluation of soc reliability
    (INFORMATIK 2006 – Informatik für Menschen, Band 1, 2006) Bernauer, Andreas; Bringmann, Oliver; Rosenstiel, Wolfgang; Bouajila, Abdelmajid; Stechele, Walter; Herkersdorf, Andreas
    This paper presents an architecture to evaluate the reliability of a systemon-chip (SoC) during its runtime that also accounts for the system's redundancy. We propose to integrate an autonomic layer into the SoC to detect the chip's current condition and instruct appropriate countermeasures. In the autonomic layer, error counters are used to count the number of errors within a fixed time interval. The counters' values accumulate into a global register representing the system's reliability. The accumulation takes into account the series and parallel composition of the system.
  • Zeitschriftenartikel
    A Fault-Tolerant Processor Architecture
    (FERS-Mitteilungen: Vol. 28, No. 1, 2010) Bouajila, Abdelmajid; Sommer, Thomas; Zeppenfeld, Johannes; Stechele, Walter; Herkersdorf, Andreas